
R2J20702NP Target Specification
REJ03G1782-0401 Rev.4.01 Page 21 of 27
Jun 17, 2010
Timing Chart
Peak Current Control
(EO-Vbe) / 2
(Internal signal)
EO
RAMP
TLD
50 ns (typ.)
Max. Duty
(Internal signal)
RES
(Internal signal)
50 ns (typ.)
0 V
VIN
SW
0 V
The high-side MOS FET is turned
off by the max. duty signal.
Note: Propagation delay is ignored.
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